Your Technology Partner and Solution Provider for

High Frequency Trading

FPGA (Versal Premium) Based HFT Products 

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General System Level Features

 

  • FPGA Based HW Module processes two ITCH feeds simultaneously
  • Scalable HW allows multiple FPGA boards to support more instruments
  • Generates single ITCH feed by combining primary and secondary feeds for accelerating WS algorithms 
  • Multiplexing two additional order lanes (unlimited TCP sessions) with FPGA orders to support fastest switch free operation
  • Recording control messaging, market data feeds, inbound and outbound orders with time stamp for analysis and back testing

Tick-to-Trade

 

  • Optimized for ultra low and deterministic latency (Parser, Synchronizer, Order Book Generation, Trigger Generation, Order Generation, TCP)
  • Built-in algorithms running on FPGA generate orders with minimum delay
  • Customer trading algorithms (under NDA) can also be implemented on FPGA for ultra-low delay T2t trading
  • Customer trading algoritms can also be implemented by customer in FPGA CPU cores (ARM A72), enabling nano-second delay SW algorithms
  • Up to 60 instruments per FPGA can be supported
  • Supports multiple TCP sessions for order generation
  • Supports HFT Tick-to-trade, SW Tick-to-Trade and Accelerator applications simultaneously

Accelerator

 

  • Optimized for ultra-low and deterministic latency (Parser, Synchronizer, Order Book Generation, Trigger Generation)
  • Price changes are sent to WS together with other information including current quantities
  • SolarFlare NIC used for direct user space DMA
  • Delay optimized SW Module receives price updates and triggers trading algorithms
  • HW Module creates the trigger in nanoseconds after the ITCH command causing it. SW Module triggers Trading Software with a minimum possible delay

Adhoc can support the selection & tuning of the Workstation on which trading algorithms are run for best performance

FPGA (Ultra Scale+) Based HFT Products 

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General System Level Features

 

  • FPGA Based HW Module processes two ITCH feeds simultaneously
  • Generates single ITCH feed by combining primary and secondary feeds for accelerating WS algorithms 
  • Multiplexing two additional order lanes (unlimited TCP sessions) with FPGA orders to support fastest switch free operation
  • Recording control messaging, market data feeds, inbound and outbound orders with time stamp for analysis and back testing

Tick-to-Trade

 

  • Optimized for ultra-low and deterministic latency (Parser, Synchronizer, Order Book Generation, Trigger Generation, Order Generation, TCP)
  • Built-in algorithms running on FPGA generate orders with minimum delay
  • Customer trading algorithms (under NDA) can also be implemented on FPGA for ultra-low delay T2t trading
  • Up to 120 instruments per FPGA can be supported
  • Supports multiple TCP sessions for order generation 
  • Supports both HFT Tick-to-trade and Accelerator applications simultaneously

Accelerator

 

  • Optimized for ultra-low and deterministic latency (Parser, Synchronizer, Order Book Generation, Trigger Generation)
  • Price changes are sent to WS together with other information including current quantities
  • SolarFlare NIC used for direct user space DMA
  • Delay-optimized SW Module receives the price updates and triggers trading algorithms
  • HW Module creates the trigger in nanoseconds after the ITCH command causing it. SW Module triggers Trading Software with a minimum possible delay

Adhoc can support the selection & tuning of the Workstation on which trading algorithms are run for the best performance

ORAK, SW-Based Ultra Low Delay HFT Accelerator Solution 

Features

  • Optimized for fast generation of order books of a large number of instruments
  • Scalable solution supporting a high number of processor cores
  • Configurable threading model (Novel thread scheduling method to optimize L1 Cache hit ratio)
  • Support for low-delay NICs (including Solarflare ultra-low latency Extended ef_vi API for EFCT architecture)
  • Flexible interfacing with algorithm software 
  • Late Joining/Market data synchronization using Glimpse Protocol 
  • Missed packet detection and recovery using MoldUDP64 re-requests
  • Targets compute-intensive algorithms for which data processing dominates I/O (with response times in the order of microseconds)
  • Capability to read .PCAP files and trigger order book building code with high precision timing
  • Arbitration between primary and secondary feeds

Precision Network Management & Analysis 

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General System Features

Measurement and Analysis System consists of the following components

  • Adhoc FPGA HW Module, where time stamping, delay measurement and flow controlled data buffering performed

  • An L1 switch/Fiber Tap capable of point-to-multipoint cross-connect (purchased seperately by the customer)

  • Software Module running on a WS for permanent storage, parsing and statistic generation  

  • Data analysis on different workstations are possible including single step exchange info investigation

FPGA Based Hardware Module Features

 

  • Receive input packets from 14 different 10 Gb SFP+ ports
  • All ports are on different time domains
  • Extremely precise time stamps (in picosecons) are issued and packets are buffered
  • Buffered packets are transferred to the WS for permanent storage with a propriatery reliable protocol

Software Module Features

 

  • Runs on WS capable of high capacity data storage
  • Receives time-stamped packets, stores them in HDD and builds a database for fast analysis
  • Flexible and reliable communication with HW Module
  • Analysis capability on stored packets

  • Delays, delay distributions and comparisons for orders from different trading devices
  • Delays and delay distributions for stock exchange feeds
  • Status building on specific times, including order book, feed times, order times and response from the stock exchange
  • Single-step analysis in time both forward and reverse direction

Market Simulator

Features

 

  • Replay of Market Data (ITCH feed) at different rates
  • Response to orders according to either predefined rules or current Market Data
  • Backtesting algorithm for market performance
  • Testing products for verification
  • Analysis of interesting conditions in the market (best operates with Adhoc Precise Network Measurement & Analysis)
  • Testing for alternative products for delay performance (best operates with Adhoc Precise Network Measurement & Analysis)

HFT Data Processing Board (DPB) - VIMK

Features

 

Very high performance FPGA board

 

  • Very small form factor to target HFT platforms
  • Scalable architecture to support different HFT requirements
  • Ultra-Low delay external SRAM capability for supporting deep order books

 

Wide Application Area

 

  • Scalable HW solution for our T2t systems (1-5 boards/equipment)
  • Scalable HW solution for HFT risk management